Instruction

Abstract

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• Also known as Machine Codes
• Bit String, which is passed to CPU, gets translated to carry out Operation
• Doesn’t specify which CPU Datapath does what, just specify what outputs are expected with a given input
• The instruction lifecycle can be broken down into Pipeline Stages

Opcode

• Config for Control Signal

Example

In MIPS, it is 6-bits, so total 2^6 → 64 different arrangements.

Parameter

• Can be Register Address, Memory Address or Immediate Value

2 Instruction Forms

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Fixed-length

• Easy Fetch & Decode
• Simplified Pipeline & Instruction-Level Parallelism

Variable-length

• More Flexible BUT Requires more steps for Fetch & Decode

Branch Instruction

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• An Instruction that causes CPU to jump to a different location in the codes of Process (进程), instead of executing instruction sequentially

Terminologies

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Single Instruction Multiple Data

• This allows one Instruction to operate on multiple data at once and have multiple outputs essentially
• This can reduce the number of instructions in a program significantly, and have more data processed without the involvement of the inefficient Main Memory

Expanding Opcode Scheme

• The Opcode in an Instruction can be extended to accommodate additional instructions in the future without changing the basic format of the instruction set

References

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• Reinventing the Processor - Youtube
• CONCURRENCY IS AN ILLUSION - YouTube