RISCV CLINT

Abstract

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• At Memory Address 0x02000000
• CLINT stands for Core-Local Interrupt Controller, a hardware component in the RISC-V architecture that provides a simple and efficient mechanism for generating interrupts within a core
• Mainly 2 features:
  1. Machine-mode Software Interrupt
     • Generated by writing to the CLINT’s msip Register
  2. Machine-mode timer interrupts
     • CLINT’s Timer Chip, which is a 32-bit countdown timer that can be programmed to generate interrupts at a specified frequency, useful for Preemptive Scheduling

Components

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MTIMECMP

• Start at Memory Address 0x02004000
• Stands for Machine Time Compare
• Register used to generate machine-level timer interrupts
• Each CPU Core has one
• Implement both periodic timers and one-shot timers

MTIME

• At Memory Address 0x02000000 + 0xBFF8 = 0x0200BFF8
• A 64-bit Register that stores the current value of the Timer Chip