Abstract


  • A tunnel connects one Pipeline Stage of an Instruction to a different pipeline stage of another instruction.
  • As shown in the diagram above, we can avoid idle time caused by the Write Back stage of the first instruction

Results can't be forwarded

If an instruction that directly follows a load instruction uses the data loaded by it, a pipeline stall is necessary. This stall occurs because loading data from memory takes one extra CPU cycle. In this case, we must apply a pipeline stall.

References