Instruction Stages

Abstract

---

• 3 main stages, Fetch, Decode & Execute
• Thew 2 main Register involved are the Instruction Register and the address register (Program Counter)

Wasted computation

Each pipeline stage is isolated and independent from each other. When one stage is running, the other stages will be idle. You can see from the animation above, when the Instruction is decoded, the instruction register is actually ready to take in the next instruction.

This can be optimised with Instruction-Level Parallelism.

Fetch

---

• Retrieve Instruction from Main Memory using Program Counter and Instruction Register

MIPS fetch stage

The instruction memory in MIPS is a sequential circuit that only gets updated with the next instruction at the next rising clock edge.

Decode

---

• Control Unit configures different parts of the CPU like ALU with the given Instruction based on the Opcode with referencing to its Instruction Set Architecture (ISA)

MIPS decode stage

Two multiplexers are used to perform the correct operand fetch for R-type and I-type instructions. The bit signal sent to RegDst is 1 for R-type and 0 for I-type. The bit signal sent to ALUSrc is 0 for R-type and 1 for I-type.

Operand Fetch

• Fetching instruction operand using the corresponding addressing mode

Execute

---

• Where the execution of Instruction is performed. See MIPS ALU for more information

Memory Access

• Retrieve required data from Main Memory for displacement addressing mode
• See MIPS read data for more information

Write Back

---

• Result is stored back into Main Memory or Register
• See Write Data for more information

MIPS register write back

RegWrite is set to 1, so data sent to WD is written to the register at WR. MemToReg is set to 1, so the ALU result is sent to WD, instead of the Read Data from the MIPS data memory.