Set Reset Latch

Abstract

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• Latch that has one set input to store a single Bit, and another reset input to reset the stored bit

  
  

• Active Set: turn on the output

• Inactive Reset: locking the state of the set input when set goes inactive

  
  

• Active Reset: turn off the output

• Inactive Set: locking the state of the reset input when the reset goes inactive

Invalid condition exists!

When both S & R are 1, the output will be 0 which is invalid

Circuit 1

• As shown in the diagram above, we can build it with one OR, one NOT and one AND
• Refer to footnote for a nice visualisation on how it works¹

Active-high Latch

• Can be built with two NOR
• Refer to footnote for a nice visualisation on how it works²
  

What is the output when the latch first turned on without any inputs?

In an ideal case, the output would switch from on to off in a very short interval. To human eyes, it would appear to be constantly on.

However, in the real world, even two identical gates with the same wiring will have slightly different gate delays. Sometimes, one gate may have a shorter delay than the other.

As a result, the output can be either 0 or 1 when the latch is first turned on.

Refer to footnote for a nice visualisation of how it works³

Circuit diagram & truth table

Q is the 1 bit storage. Below is a block diagram:

Gated S-R Latch

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• Active-high Latch made with Steering Gate and active-low latch
• Only active when EN is high

Footnotes

1. Circuit 1 (From 1:15 to 2:36) ↩

2. Circuit 2 (From 2:57 to 4:33) ↩

3. Circuit 2 Race Condition (From 5:56 to 7:35) ↩