Abstract
- When the CPU requests data that is not found in the CPU Cache
- It requires fetching the data from the slower Main Memory, incurring a higher access time compared to a Cache Hit
Important
The total miss is the sum of Compulsory Miss, Conflict Miss and Capacity Miss.
Capacity miss is the total miss excluding cold miss, when conflict miss is zero. So capacity miss only happens on Fully Associative Cache.
Compulsory Miss
- Also known as cold start miss or first reference miss
- First time accessing the data
Conflict Miss
- Also known as collision miss or interference miss
- When multiple data mapped to the same Cache Line
Important
This can be reduced with Set Associative Cache. A Direct Mapped Cache of size has about the same miss rate as a 2-way set associative cache of size .
Important
For the same cache size, conflict miss goes down with increasing associativity. Conflict miss is for Fully Associative Cache.
Capacity Miss
- When data is discarded from CPU Cache as the cpu cache is running out of space
Important
For the same cache size, capacity miss remains the same irrespective of associativity. Capacity miss decreases with increasing cache size.
Cache Write Miss
- The data isn’t in the CPU Cache when we want to write data back
Write Allocate
- We can load the entire Cache Line into CPU Cache to write the data
- We can use Write-through Cache Strategy or Write-back Cache Strategy to write back the data to the Main Memory
- Or we can don’t load the cache line to the cpu cache and use Write-around Cache Strategy