Pipelining

Abstract

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• Increases the execution throughput of the machine by processing multiple independent Instruction Stages simultaneously, supporting Instruction-Level Parallelism.

Important

Pipelining does not reduce the latency of a single instruction, but it increases the throughput of the entire workload.

2 stages in one slot!

Since the register file is very fast, the ID stage of the second instruction and the WB stage of the first instruction can be executed concurrently. This is possible because writes to the register file always precede reads.

Pipeline Width

• The Instruction-Level Parallelism capabilities - how many Instruction can be run in parallel in the same time

References

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• CPU Pipelining - The cool way your CPU avoids idle time!